Several non-volatile memory (NVM) devices have been introduced that reduce memory size by facilitating the storage of multiple bits per NVM cell. For example, a 2-bit non-volatile semiconductor memory transistor including oxide-nitride-oxide storage structure has been described in U.S. Pat. No. 5,768,192, to Eitan. A problem with these types of 2-bit NVM devices is that they require a special photolithographic fabrication procedure (process flow), and therefore are not conducive to use as embedded NVM memory in larger circuits (e.g., system-on-a-chip devices). Further, the operating voltages (i.e., to perform program/erase operations) is typically much higher than the operating voltage of a modern CMOS integrated circuit (IC).
Another type of 2-bit NVM device disclosed, for example, in U.S. Patent Application No. 2003/222,303, to Fukuda et al. utilizes special (e.g., silicon nitride) storage structures formed inside silicon-oxide sidewall spacers to store data. This type of 2-bit NVM may be utilized to provide an embedded NVM array in a larger integrated circuit (IC), but requires substantial modification to an existing (e.g., CMOS) process flow in order to form both the storage structures and the sidewall spacers. Further, such NVM cells can be relatively unreliable due to misalignment between the relatively small storage structures and associated source/drain regions, which can lead to process related variations that inevitably lead to strong Vt (threshold voltage) and programmability spread.
What is needed is a low-cost embedded NVM cell array that can be implemented using a minimum of additional masks to an existing CMOS process flow, that would not require high operating voltages (i.e., less than 6V), and that would exhibit a reliability that is equal to or greater than existing embedded NVM solutions.